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| 01/08/08 1 pd-60333 ir3822mpbf highly integrated 4a wide-input voltage, sy nchronous buck regulator features ? wide input voltage range 2.5v to 21v ? wide output voltage range 0.6v to 12v ? continuous 4a load capability ? 600khz high frequency operation ? programmable over-current protection ? programmable pgood output ? hiccup current limit ? precision reference voltage (0.6v) ? programmable soft-start ? pre-bias start-up ? thermal protection ? thermally enhanced package ? small size 5mmx6mm qfn ? pb-free (rohs compliant) fig. 1. typical application diagram description the ir3822 sup ir buck tm is an easy-to-use, fully integrated and highly efficient dc/dc regulator. the onboard switching controller and mosfets make the ir3822 a space-efficient solution, providing accurate power delivery for low output voltage applications. the ir3822 operates from a single 4.5v to 14v input supply and generates an output voltage adjustable from 0.6v to 0.75*vin at loads up to 4a. a versatile regulator offering programmability of startup time, power good threshold and current limit, the ir3822?s fixed 600khz switching frequency allows the use of small external components. the ir3822 also features important protection functions, such as pre-bias startup, hiccup current limit and thermal shutdown to provide the required system level security in the event of fault conditions. applications ? distributed point-of-loads ? server and workstations ? embedded systems ? storage systems ? ddr applications ? graphics cards ? game consoles ? computing peripheral voltage regulators sup ir buck tm
01/08/08 2 pd-60333 ir3822mpbf package information 5mm x 6mm power qfn 12 v in 11 sw 10 pgnd 15 agnd 1 23 4 5 6 7 8 9 14 13 vsns fb comp agnd agnd ss ocset pgood v cc v c hg fig. 2: package outline (top view) w / c 2 w / c 35 o pcb j o ja = = - absolute maximum ratings (voltages referenced to gnd) ?v in supply voltage -0.3v to 24v ? vcc supply voltage -0.3v to 16v ? vc supply voltage -0.3v to 30v ? sw -0.3v to 30v ? pgood -0.3v to 16v ? fb,comp,ss,vsns -0.3v to 3.5v ?ocset 10ma ? agnd to pgnd -0.3v to +0.3v ? storage temperature range -65 c to 150 c ? operating junction temperature range -40 c to 150 c ? esd classification jedec, jesd22-a114 ? moisture sensitivity level jedec level 3 @ 260 o c caution: stresses beyond those listed under ?absolute maxi mum rating? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational secti ons of the specifications is not impl ied. exposure to ?absolute maximum rating? conditions for extended periods may affect device reliability. 4000 parts per reel --------------- parts per tube 15 pin count ir3822mtrpbf package description m pkg desig ordering information 01/08/08 3 pd-60333 ir3822mpbf block diagram fig. 3. simplified block diagram of the ir3822. 01/08/08 4 pd-60333 ir3822mpbf pin description pin name description 1 vsns pgood sense pin. use two external resistors to program the power good threshold. 2 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 3 comp output of error amplifier. 4 agnd signal ground for internal reference and control circuitry. 5 agnd signal ground for internal reference and control circuitry. 6 ss/sd soft start / shutdown. this pin provides user programmable soft-start function. connect an external capacitor from this pin to signal ground (agnd) to set the start up time of the output voltage. the converter can be shutdown by pulling this pin below 0.3v. 7 ocset current limit set point. a resistor from this pin to sw pin will set the current limit threshold. 8 v cc this pin provides biasing voltage for the internal blocks of the ic. it also powers the low side driver. a minimum of 0.1uf, high frequency capacitor must be connected from this pin to power ground (pgnd). 9 pgood power good status pin. output is open collector. connect a pull up resistor from this pin to vcc. 10 pgnd power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 11 sw switch node. this pin is connected to the output inductor 12 v in input voltage connection pin 13 hg this pin is connected to the high side mosfet gate. connect a small capacitor from this pin to switch node (sw). 14 v c this pin powers the high side driver and must be connected to a voltage higher than input voltage. a minimum of 0.1uf high frequency capacitor must be connected from this pin to the power ground (pgnd). 15 agnd signal ground for internal reference and control circuitry. pins 4, 5 and 15 need to be connected together on system board. 01/08/08 5 pd-60333 ir3822mpbf recommended operating conditions parameter symbol test condition min typ max units power loss power loss p loss vcc=v in =12v, vc=24v, v o =1.8v, i o =4a, l=1.5uh, note3 1.5 w mosfet r ds(on) top switch r ds(on)_top i d =6a, tj(mosfet)=25 o c 18 23 bottom switch r ds(on)_bot i d =6a, tj(mosfet)=25 o c 18 23 m reference voltage feedback voltage v fb 0.6 v 0 o c 01/08/08 7 pd-60333 ir3822mpbf typical operating characteristics (-40 o c - 125 o c) icc(static) 7.0 8.0 9.0 10.0 11.0 12.0 13.0 -40 -20 0 20 40 60 80 100 120 temp[oc] [ma] ic(static) 2.0 3.0 4.0 5.0 6.0 7.0 -40-20 0 20406080100120 temp[oc] [ma] icc(dynamic) 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 -40 -20 0 20 40 60 80 100 120 temp[oc] [ma] ic(dynamic) 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 -40 -20 0 20 40 60 80 100 120 temp[oc] [m a] vfb 585.0 590.0 595.0 600.0 605.0 -40 -20 0 20 40 60 80 100 120 temp[oc] [mv] iss 15.0 17.0 19.0 21.0 23.0 25.0 27.0 -40-20 0 20406080100120 temp[oc] [u a ] transconductance 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 -40 -20 0 20 40 60 80 100 120 temp[oc] [mmho] iocset 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 -40 -20 0 20 40 60 80 100 120 temp[oc] [u a ] 01/08/08 8 pd-60333 ir3822mpbf circuit description theory of operation the ir3822 is a voltage mode pwm synchronous regulator and operates with a fixed 600khz switching frequency, allowing the use of small external components. the output voltage is set by feedback pin (fb) and the internal reference voltage (0.6v). these are two inputs to error amplifier. the error signal between these two inputs is amplified and it is compared to a fixed frequency linear sawtooth ramp. a trailing edge modulation is used for generating fixed frequency pulses (pwm) which drives the internal n-channel mosfets. the internal oscillator circuit uses on-chip circuitry, eliminating the need for external components. the ir3822 operates with single input voltage from 4.5v to 14v allowing an extended operating input voltage range. the over-current protection is performed by sensing current through the r ds(on) of low side mosfet. this method enhances the converter?s efficiency and reduces cost by eliminating a current sense resistor. the current limit is programmable by using an external resistor. under-voltage lockout the under-voltage lockout circuit monitors the two input supplies (vcc and vc) and assures that the mosfet driver outputs remain in the off state whenever the supply voltage drops below set thresholds. lockout occurs if vcc or vc fall below 4.3v and 3.3v respectively. normal operation resumes once vcc and vc rise above the set values. thermal shutdown temperature sensing is provided inside the ir3822. the trip threshold is typically set to 140 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets. thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops within the operating range. there is a 20 o c hysteresis in the thermal shutdown threshold. pre-bias startup the ir3822 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet off until the first gate signal for control mosfet is generated. figure 4 shows a typical pre-bias condition at start up. depending on system configuration, a specific amount of output capacitors may be required to prevent discharging the output voltage. fig. 4: pre-bias start up vo time v pre-bias voltage shutdown the output can be shutdown by pulling the soft- start pin below 0.3v. this can easily be done by using an external small signal transistor. during shutdown both mosfet drivers will be turned off. normal operation will resume by cycling soft start pin. power good the ir3822 provides an open collector power good signal which reports the status of the output. the output is sensed through the dedicated vsns pin. the power good threshold can be externally programmed using two external resistors. the power good comparator is internally set to 0.38v (typical). 01/08/08 9 pd-60333 ir3822mpbf soft-start the ir3822 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. to ensure correct start-up, the soft-start sequence initiates when vcc and vc rise above their threshold and generate the power on ready (por) signal. the soft-start function operates by sourcing current to charge an external capacitor to about 3v. initially, the soft-start function clamps the output of error amplifier by injecting a current (40ua) into the fb pin and generates a voltage about 0.96v (40ux24k) across the negative input of error amplifier (see figure 5). the magnitude of the injected current is inversely proportional to the voltage at the soft-start pin. as the soft-start voltage ramps up, the injected current decreases linearly and so does the voltage at negative input of error amplifier. when the soft-start capacitor is around 1v, the voltage at the positive input of the error amplifier is approximately 0.6v. the output of error amplif ier will start increasing and generating the first pwm signal. as the soft- start capacitor voltage continues to rise up, the current flowing into the fb pin will keep decreasing. the feedback voltage increases linearly as the soft start voltage ramps up. when soft-start voltage is around 2v, the output voltage reaches the steady state and the injected current is zero . figure 6 shows the theoretical operating waveforms during soft-start. the output voltage start-up time is the time period when soft-start capacitor voltage increases from 1v to 2v. the start-up time will be dependent on the size of the external soft-start capacitor and can be estimated by: fig. 5: soft-start circuit for ir3822 fig. 6: theoretical operation waveforms during soft-start 20ua 40ua por error amp ss/sd fb comp 24k 0.6v 24k 3v soft-start voltage voltage at negative input of error amp voltage at fb pin current flowing into fb pin 40ua 0ua 0v 0.6v ? 0.96v 0.6v 0v 3v ? 2v ? 1v output of uvlo por for a given start-up time, the soft-start capacitor can be estimated as: v 1 v 2 c t a 20 ss start ? = ? ) 1 --( ms t a 20 c start ss ) ( * ? 01/08/08 10 pd-60333 ir3822mpbf over-current protection the over-current protection is performed by sensing current through the r ds(on) of the low side mosfet. this method enhances the converter?s efficiency and reduces cost by eliminating a current sense resistor. as shown in figure 7, an external resistor (r set ) is connected between ocset pin and the inductor point which sets the current limit set point. the internal current source develops a voltage across r set . when the low side mosfet is turned on, the inductor current flows through the q2 and results a voltage which is given by: fig. 7: connection of over current sensing resistor fig. 8: 3ua current source for discharging soft-start capacitor during hiccup an over-current is detected if the ocset pin goes below ground. this trips the ocp comparator and cycles the soft start function in hiccup mode. the hiccup is performed by charging and discharging the soft-start capacitor in a certain slope rate. as shown in figure 8 a 3ua current source is used to discharge the soft-start capacitor. the ocp comparator resets after every soft start cycle. the converter stays in this mode until the overload or short circuit is removed. the converter will automatically recover. ) ) --( i (r ) r (i v l ds(on) ocset ocset ocset 2 ? ? ? = 0 ) i (r ) r (i v l ds(on) ocset ocset ocset = ? ? ? = ) 3 --( r i r i i on ds ocset ocset critical l set ) ( ) ( ? = = fig. 9: ocset pin during normal condition ch1: inductor point, ch3:ocset the value of r set should be checked in an actual circuit to ensure that the over-current protection circuit activates as expected. the ir3822 current limit is designed primarily as disaster preventing, and doesn't operate as a precision current regulator. the critical inductor current can be calculated by setting: i ocset *r ocset blanking time deadtime clamp voltage the ocp circuit starts sampling current when the low gate drive is about 3v. the ocset pin is internally clamped about 1.5v during on time of high side gate to prevent false trigging, figure 9 shows the ocset pin during one switching cycle. as shown, there is about 150ns delay to mask the dead time. since this node contains switching noises, this delay also functions as a filter. 01/08/08 11 pd-60333 ir3822mpbf application information design example: the following example is a typical application for the ir3822. the application circuit is shown in page 17. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6v. the divider is ratioed to provide 0.6v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: when an external resistor divider is connected to the output as shown in figure 10. equation (4) can be rewritten as: for the calculated values of r 8 and r 9 see feedback compensation section. khz 600 f mv 30 v a 4 i v 8 . 1 v ) max v, 2 . 13 v,( 12 v s o o o in = = = = ) 4 --( r r 1 v v 9 8 ref o ? ? ? ? ? ? ? ? + ? = fig. 10: typical application of the ir3822 for programming the output voltage ) 5 --( v v v r r ref o ref 8 9 ? ? ? ? ? ? ? ? ? ? = soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated by using: where t start is the desired start-up time (ms) for a start-up time of 11ms, the soft-start capacitor will be 0.22uf. vc supply for single input voltage to drive the high-side switch, it is necessary to supply a gate voltage at least 4v greater than the bus voltage. this is achieved by using a charge pump configuration as shown in figure 11. this method is simple and inexpensive. the operation of the circuit is as follows: when the lower mosfet is turned on, the capacitor (c1) is pulled down to ground and charges, up to v bus value, through the diode (d1). the bus voltage will be added to this voltage when upper mosfet turns on in next cycle, and providing supply voltage (vc) through diode (d2). vc is approximately: capacitors in the range of 0.1uf are generally adequate for most applications. the diodes must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into v bus . the diodes need to be able to block the full power rail voltage, which is seen when the high-side mosfet is switched on. for low-voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up. fig. 11: charge pump circuit to generate vc voltage ( ) ) 6 --( v v v 2 v 2 d 1 d bus c + ? ? ? * ? ir3822 01/08/08 12 pd-60333 ir3822mpbf input capacitor selection the input filter capacitor should be selected based on how much ripple the supply can tolerate on the dc input line. the ripple current generated during the on time of upper mosfet should be provided by the input capacitor. the rms value of this ripple is expressed by: where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. for io=4a and d=0.15, the i rms =1.43a. ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. use 3x10uf, 16v ceramic capacitors from panasonic. inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. a low inductor value causes a large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor . the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following: where: ) 7 --( d 1 d i i o rms ) ( ? ? ? = in o v v d = s o in f 1 d t t i l v v ? = ? = ? ; ) ( i () ) 8 --( f i v v v v l s in o o in * ? ? ? = cycle duty d time on turn t frequency switching f current ripple inductor i voltage output v voltage input maximum v s o in = = = = = = if , then the output inductor will be: l = 1.50uh delta mpo104 series provides a range of inductors in different values and low profile suitable for large currents. output capacitor selection the voltage ripple and transient requirements determine the output capacitors? type and values. the criteria is normally based on the value of the effective series resistance (esr). however the actual capacitance value and the equivalent series inductance (esl) are other contributing components. these components can be described as: since the output capacitor has a major role in the overall performance of the converter and determine the result of transient response, selection of the capacitor is critical. the ir3822 can perform well with all types of capacitors. as a rule the capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy stability requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. therefore, a ceramic capacitor is selected due to its low esr and small size. four of the panasonic ecj2fb0j226m (22uf, 6.3v, x5r and eia 0805 case size) are a good choice. in the case of tantalum or low esr electrolytic capacitors, the esr dominates the output voltage ripple, equation (9) can be used to calculate the required esr for the specific voltage ripple. ) %( 40 o i i current ripple inductor i ripple voltage output v f c 8 i v esl l v v -(9) - esr i v v v v v l o s o l c o in esl o l esr o c o esl o esr o o = = = ? ? ? ? ? ? = = + + = * * * * ) ( ) ( ) ( ) ( ) ( ) ( 01/08/08 13 pd-60333 ir3822mpbf feedback compensation the ir3822 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highes t 0db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, ? 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 13). the resonant frequency of the lc filter expressed as follows: figure 13 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system risks being unstable. the ir3822?s error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control or ac phase compensation. the error amplifier can be compensated either in type ii or type iii compensation. when it is used in type ii compensation the transconductance properties of the error amplifier become evident and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 14. this method requires that the output capacitor should have enough esr to satisfy stability requirements. in general the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. (11) - - - c l 2 1 f o o lc = gain f lc 0db phase 0 f lc -180 frequency frequency -40db/decade fig. 13: gain and phase of lc filter the esr zero of the output capacitor expressed as follows: the transfer function (ve/vo) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: the gain is determined by the voltage divider and error amplifier?s transconductance gain. first select the desired zero-crossover frequency (fo): use the following equation to calculate r3: where: v in = maximum input voltage v osc = oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 8 and r 9 = feedback resistor dividers g m = error amplifier transconductance (12 ) - - - c esr 2 1 f o esr * * ? = fig. 14: typeii compensation network and its asymptotic gain plot (13) - - - sc c sr 1 * r r r * g ) s ( h 4 4 3 8 9 9 m + + = () [] (15) - - - c r 2 1 f (14) - - - r * r r r g s h 4 3 z 3 8 9 9 m * * * = ? ? ? ? ? ? ? ? + = ( ) s o esr o f 1/10 ~ 1/5 f and f f * > (16) - - - g * r * f * v ) r r ( * f * f * v r m 9 2 lc in 9 8 esr o osc 3 + = ve v out v ref r 9 r 8 r 3 c 4 e/a f z h(s) db frequency gain(db) fb comp c pole 01/08/08 14 pd-60333 ir3822mpbf to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: use equations (15) and (16) to calculate c4. one more capacitor is sometimes added in parallel with c4 and r3. this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole : for a general solution for unconditional stability for any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensat ion network (type iii). the typically used compensation network for voltage-mode controller is shown in figure 15. in such a configuration, the transfer function is given by: the error amplifier gain is independent of the transconductance under the following condition: by replacing z in and z f according to figure 15, the transformer function can be expressed as: (17) - - - c l 2 1 75 0 f f 75 f o o z lc z * * . % = = as known, the transconductance amplifier has high impedance (current source) output, therefore, consideration should be taken when loading the error amplifier output. it may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two zeros and they are expressed as follows: cross over frequency is expressed as: c c c c r 2 1 f pole 4 pole 4 3 p + = * * * 2 f f for f r * 1 c 1 f r 1 c s p s 3 4 s 3 pole << ? ? = * * * fig.15: compensation network with local feedback and its asymptotic gain plot in m f m o e z g 1 z g 1 v v + ? = ( ) [] ) ( * * * ) ( * ) ( ) ( 7 10 3 4 3 4 3 10 8 7 4 3 3 4 8 c sr 1 c c c c sr 1 r r sc 1 c sr 1 c c sr 1 s h + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + = 8 7 10 8 7 2 z 4 3 1 z 3 3 3 4 3 4 3 3 p 7 10 2 p 1 p r c 2 1 r r c 2 1 f c r 2 1 f c r 2 1 c c c c r 2 1 f c r 2 1 f 0 f * * ) ( * * * * * * * * * * ? + = = ? ? ? ? ? ? ? ? ? + = = = o o osc in 7 3 o c l 2 1 v v c r f * * * * * = (18) - - - 1 z * g and 1 z * g in m f m >> >> v out v ref r 9 r 8 r 10 c 7 c 3 c 4 r 3 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp 01/08/08 15 pd-60333 ir3822mpbf based on the frequency of the zero generated by the output capacitor and its esr versus crossover frequency, the compensation type can be different. the table below shows the compensation types and location of crossover frequency. the dc gain will be large enough to provide high dc-regulation accuracy (typically -5db to -12db). the phase margin should be greater than 45 o for overall stability. desired phase boost: ceramic f lc 01/08/08 17 pd-60333 ir3822mpbf typical application for ir3822 12v to 1.8v @ 4a fig.16: typical application circuit for 12v to 1.8v at 4a using ceramic output capacitors 01/08/08 18 pd-60333 ir3822mpbf pcb metal and components placement the lead lands (the 11 ic pins) width should be equal to the nominal part lead width. the minimum lead-to-lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. the outboard extension ensures a large and inspectable toe fillet. the pad lands (the 4 big pads other than the 11 ic pins) length and width should be equal to maximum part pad length and width. however, the minimum metal-to-metal spacing should be no less than 0.17mm for 2 oz. copper; no less than 0.1mm for 1 oz. copper and no less than 0.23mm for 3 oz. copper. 01/08/08 19 pd-60333 ir3822mpbf solder resist it is recommended that the lead lands are non solder mask defined (nsmd). the solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure nsmd pads. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. 01/08/08 20 pd-60333 ir3822mpbf stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. reducing the amount of solder deposited will minimize the occurrences of lead shorts. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. 01/08/08 21 pd-60333 ir3822mpbf ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the consumer market. visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 10/07 |
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